A Clock Generator Driven by a Unified-CBiCMOS Buffer Driver for High Speed and Low Energy Operation

A new operation mode for a lateral unified-complementary BiCMOS (hereafter abbreviated as U-CBiCMOS) buffer driver based on a partially depleted CMOS/SOI process is proposed. The scheme utilizes a gated npn or pnp BJT inherent to a nor p-channel MOSFET. Forward current is applied to the base terminal of the channel MOSFET, with a normal pull-up or pull-down MOSFET as a current source, where each drain terminal is connected to the corresponding base terminal of the buffer. A new logic scheme is designed to feed an input signal to the gates of the pull-up and pull-down MOSFETs, rather than to those of the nand p-channel MOSFETs as in our previous work, while also keeping both the nand p-channel MOSFETs inactive and activating either the lateral npn or pnp BJT. A clock generator composing of the ring oscillator with a 21-stage CMOS inverter driven by the U-CBiCMOS buffer driver is designed. Circuit simulation using 0.35μm BSIM3v3 model parameters for the MOSFETs and a current gain of βF = 100 for the BJTs revealed the speed of the U-CBiCMOS buffer driver to be more than 4 times faster than that of an equivalent 4-stage CMOS inverter designed on the basis of logical effort for driving a load capacitance of 1.417 pF at Vdd = 1 V.